In this tutorial, we are going to write Verilog code to enable the Pulse-Width Modulation (PWM) in FPGA (DE0-Nano). The clock frequency is 50MHz. The period of GPIO signals is controlled by the counter[27], i.e. (1/50E6)*2^27 ~ 2.6sec. As the threshold point is marked by counter[27], the Most Significant Bit (MSB) is OFF when the counter is below 2^27 / 2 = 67108864. Otherwise, the MSB is ON. The light intensity of the LED should vary continuously.
1) Build the above circuit
2) Install Quartus II 20.1
3) Connect the FPGA to your PC and install Altera USB Blast Driver
If you are using Win 10 or above, please restart the computer in the “options menu” mode.
=> Press the key combination Win+R. The command of activating the “options menu” is shutdown.exe /r /o /f /t 00
=> In the “Options menu”, click “Troubleshoot” and then “Advanced options”.
=> Click on the “startup settings” and then “reboot”
=> After another reboot, press the number key. Option 7 should appear: “Disable driver signature enforcement”. This hides the driver check and allows you to install the unsigned driver.
=> In "Device Manager", find the USB port and then right-click "Update Driver"
=> Specify the location of the driver (e.g. C:\altera\10.1\quartus\drivers\usb-blaster) and then install it
4) In the Terasic CD, go to C:\your own directory\DE0\DE0-Nano_v.1.2.8_SystemCD\Demonstration\DE0_NANO_default
5) Open DE0_NANO QPF File.
6) Check if the pin planner is okay (find "Assignments" in Quartus II)
7) Paste the following Verilog code and click "Start complication"
module DE0_NANO(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////////// EPCS //////////
EPCS_ASDO,
EPCS_DATA0,
EPCS_DCLK,
EPCS_NCSO,
//////////// Accelerometer and EEPROM //////////
G_SENSOR_CS_N,
G_SENSOR_INT,
I2C_SCLK,
I2C_SDAT,
//////////// ADC //////////
ADC_CS_N,
ADC_SADDR,
ADC_SCLK,
ADC_SDAT,
//////////// 2x13 GPIO Header //////////
GPIO_2,
GPIO_2_IN,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0_D,
GPIO_0_IN,
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
GPIO_1_D,
GPIO_1_IN,
);
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output [1:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
//////////// EPCS //////////
output EPCS_ASDO;
input EPCS_DATA0;
output EPCS_DCLK;
output EPCS_NCSO;
//////////// Accelerometer and EEPROM //////////
output G_SENSOR_CS_N;
input G_SENSOR_INT;
output I2C_SCLK;
inout I2C_SDAT;
//////////// ADC //////////
output ADC_CS_N;
output ADC_SADDR;
output ADC_SCLK;
input ADC_SDAT;
//////////// 2x13 GPIO Header //////////
inout [12:0] GPIO_2;
input [2:0] GPIO_2_IN;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0_D;
input [1:0] GPIO_0_IN;
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1_D;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire trigger;
reg [27:0] counter;
reg [5:0] PWM_adj;
reg [6:0] PWM_width;
reg [7:0] GPIO_0_D;
always @(posedge CLOCK_50)
begin
counter <= counter + 1;
PWM_width <= PWM_width[5:0] + PWM_adj;
if(counter[27])
PWM_adj <= counter[26:21];
else
PWM_adj <= ~ counter[26:21];
GPIO_0_D[3] <= PWM_width[6];
end
endmodule
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